1. Field of the Invention
The present invention relates to a method of making a semiconductor memory device, and more particularly to a method of making a semiconductor memory device, capable of increasing the storage node surface area and thus the cell capacitance.
2. Description of the Prior Art
The development of manufacturing techniques for semiconductor devices has, promoted the development of high capacitance dynamic random access memories (DRAMs) of high capacitance. For this reason, the physical area occupied by one memory cell in a semiconductor device is inevitably on a decreasing trend.
Generally, a DRAM devices comprises memory cells each including a metal oxide semiconductor capacitor and a metal oxide semiconductor (MOS) transmission transistor. The signal level upon reading information stored in memory cells depends on the amount of charge accumulated in the MOS capacitors. As a result, the effective capacitor area can not be greatly reduced, taking into consideration the requirement that the area occupied by the memory cells should be reduced for achieving the high capacitance of DRAM cells.
An important problem encountered in achieving the high capacitance of DRAM cells is how to make the capacitance of memory cells increase under the condition that the area occupied by the memory cells is minimized.
As a method for increasing the capacitance of memory cells without an increase in the area occupied by the memory cells, there have been known a method for making a capacitor insulating layer very thin, a method for increasing the dielectric constant of capacitor insulating layer and a method for increasing the capacitor area.
Among the methods for increasing the capacitance area, however, the method for making a capacitor insulating layer very thin encounters a limitation on the reliance of a DRAM device manufactured. For increasing the dielectric constant, the capacitor insulating layer may be made of Si.sub.3 N.sub.4, in place of SiO.sub.2. However, this method also encounters a problem as to the reliance of DRAM device.
Accordingly, a stacked capacitor structure and a trenched capacitor structure have been also been proposed as methods capable of increasing the cell capacitance without an increase in the area occupied by the memory cells.
The present invention is concerned with a method of making a DRAM device with a structure in which a storage node has a plurality of pillars so that its surface area is increased, thereby enabling the cell capacitance to increase.
FIGS. 1A to 1D are sectional views illustrating a method for making a DRAM device with a conventional structure in which a storage node has opposite side walls for increasing the cell capacitance. Basically, the method comprises the steps of forming a MOS transistor, forming a bit line over a bit line contact, and forming a stacked capacitor.
In accordance with the method, first, on a silicon substrate 11 which has a field oxide film 12 for isolating elements from one another are formed an impurity region 13 of a conductivity type opposite to that of the silicon substrate 11, a gate 14 and a gate insulating film 15, in this order, so as to form a MOS transistor, as shown in FIG. 1A.
Thereafter, a bit line contact is formed by removing a portion of the gate insulating film 15 corresponding to a region at which a bit line will be formed. Over the bit line contact, a bit line 16 and a bit line insulating film 17 are formed.
As the step of forming a capacitor, a polysilicon film is selectively deposited only over the capacitor contact, so as to form a polysilicon plug 18. Over the resultant entire exposed surface after the formation of plug 18 are coated a nitride film 19 and an oxide film 20, in this order. Thereafter, a photoresist 21 is coated. The photoresist 21 is then subjected to a patterning for forming a pillar forming pattern.
By using the photoresist pattern as a mask, the oxide film 20 and the nitride film 19 are sequentially etched to form pillars, as shown in FIG. 1B. Subsequently, the photoresist pattern is removed. For etching, the nitride film 19 should have a high etch selectivity, as compared with the oxide film 20.
Over the resultant entire exposed surface, a polysilicon film 22 for a storage node is then deposited, as shown in FIG. 1C. The polysilicon film 22 is subjected to a smoothing treatment using an oxide film or a silicon-on-glass (SOG) film. Thereafter, the polysilicon film 22 is etched back, so as to remove its portion disposed over the oxide film 20. As a result, neighboring elements are isolated from each other.
As shown in FIG. 1D, the nitride film 19 disposed over the oxide film 20 is then removed. Although not shown, a dielectric film is formed over the polysilicon film 22. Finally, a formation of a plate node on the dielectric film is carried out. Thus, a capacitor is made.
However, this conventional method wherein the storage node having a side wall structure is formed for increasing the cell capacitance involves the smoothing treatment for nitride film which results in a difficulty in carrying out the method. Moreover, the selective deposition of polysilicon film for forming the plug only at the capacitor contact requires a sophisticated technique and an expensive equipment,
The conventional method also has a difficulty in achieving a mass production, since the nitride film requires a high etch selectivity over the oxide film and the pillars should be shaped to be perpendicular to the substrate.
Referring to FIGS. 2A to 2C, there is illustrate a method of making a DRAM device with another conventional structure. In this conventional method, a knurled surface is formed at the surface of a storage node, so as to increase the cell capacitance.
FIGS. 2A to 2C illustrate a part of the processes for making a DRAM device, that is, a process for forming a capacitor after the formation of a transistor and a bit line on a silicon substrate 31. The formation of a transistor and a bit line is carried out, in a similar manner to that illustrated in FIGS. 1A to 1D. For 20 simplify the illustration, the transistor and bit line are not shown and only the capacitor is shown in FIG. 2A to
After the formation of transistor and bit line, an insulating film 33 is formed over the silicon substrate 31 having an impurity region 32, as shown in FIG. 2A. The insulating film 33 is then partially etched to expose the impurity region 32 to external. Accordingly, a capacitor contact 34 is formed over the exposed portion of impurity region 32. Over the resultant entire exposed surface, a doped polysilicon film 35 is deposited to have a predetermined thickness, using a low pressure chemical vapor deposition (LPCVD) method which is carried out at a temperature of 600.degree. C. The polysilicon layer 35 is then subjected to a patterning for forming a capacitor contact 34 thereon.
Thereafter, another polysilicon film 36 is deposited over the resultant entire exposed surface, as shown in FIG. 2B. The deposition is achieved by using a SiH.sub.4 gas diluted with helium (He) (about 20%) at a pressure of 1 Tort and a temperature of 550.degree. C.
The polysilicon film 36 is then etched back, using an anisotropic dry etch method utilizing a HBr gas, so as to remove it except for its portion contacting with the side walls of the patterned polysilicon film 35, as shown in FIG. 2C. As a result, a storage node having a knurled surface is formed in a self-aligned manner.
Although not shown, a dielectric film is then formed over the entire surface of the storage node, Finally, a formation of a plate node on the dielectric film is carried out. Thus, a capacitor is made.
Assuming the knurled surface of the Storage node shown in FIG. 2C have a plurality of hemisphere knurls, the ratio of the total surface area of the knurled storage node to the surface area of the storage node having a planar surface can be expressed by the following equation: ##EQU1##
As apparent from the equation, it is difficult to increase the surface area of the knurled storage node in excess of two times the surface area of the planar storage node. Consequently, the method for increasing the surface area of storage node by forming a knurled surface at the storage node has a limitation on an increase in cell capacitance.